A High-Performance 0.25-μm CMOS Technology: II—Technology
- Bijan Davari
- Wen-Hsing Chang
- et al.
- 1992
- IEEE T-ED
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85 results for Karen Petrillo
Sub-μm, planarized, Nb-AlOx-Nb Josephson process for 125 mm wafers developed in partnership with Si technology
- M.B. Ketchen
- D.J. Pearson
- et al.
- 1991
- Applied Physics Letters
A Highly Latchup-Immune 1-μm CMOS Technology Fabricated with 1-MeV Ion Implantation and Self-Aligned TiSi2
- Fang-Shi J. Lai
- L.K. Wang
- et al.
- 1986
- IEEE T-ED
A Self-Aligned 1-μm-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy
- Yuan Taur
- Genda J. Hu
- et al.
- 1985
- IEEE T-ED
A Self-Aligned 1-μm-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy
- Yuan Taur
- Genda J. Hu
- et al.
- 1985
- IEEE Journal of Solid-State Circuits