Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
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58 results for Terence B. Hook
Impact of hot-carrier degradation on drain-induced barrier lowering in multifin SOI n-Channel FinFETs with self-heating
- Charu Gupta
- Anshul Gupta
- et al.
- 2020
- IEEE T-ED
Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating
- Anshul Gupta
- Charu Gupta
- et al.
- 2019
- IEEE T-ED
Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
- Ishita Jain
- Anshul Gupta
- et al.
- 2018
- IEEE T-ED
OFF-State Leakage and Performance Variations Associated with Germanium Preamorphization Implant in Silicon-Germanium Channel pFET
- Vishal A. Tiwari
- Rama Divakaruni
- et al.
- 2018
- IEEE T-ED
Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyond
- Nicholas A. Lanzillo
- Koichi Motoyama
- et al.
- 2018
- IITC 2018
Evaluation of 10-nm Bulk FinFET RF Performance - Conventional Versus NC-FinFET
- R. Singh
- K. Aditya
- et al.
- 2018
- IEEE Electron Device Letters
Series Resistance Reduction with Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET
- Anil K. Bansal
- Manoj Kumar
- et al.
- 2018
- IEEE T-ED
Advanced FDSOI design: The U-channel device for 7nm node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2017
- S3S 2017
3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes
- Anil K. Bansal
- Charu Gupta
- et al.
- 2018
- IEEE T-ED