Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
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58 results for Terence B. Hook
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
Technology elements of a common platform bulk foundry offering (invited)
- P. Gilbert
- A. Steegen
- et al.
- 2007
- IEDM 2007
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
Evaluation of 10-nm Bulk FinFET RF Performance - Conventional Versus NC-FinFET
- R. Singh
- K. Aditya
- et al.
- 2018
- IEEE Electron Device Letters
Efficient and accurate schematic transistor model of FinFET parasitic elements
- Ning Lu
- Terence B. Hook
- et al.
- 2013
- IEEE Electron Device Letters
Analysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond
- Jeffrey B. Johnson
- Terence B. Hook
- et al.
- 2008
- IEEE Electron Device Letters
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021