Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2018
- IEEE J-EDS
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58 results for Terence B. Hook
Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs
- R. Singh
- Anshul Gupta
- et al.
- 2017
- IEEE T-ED
7-nm Nanowire FET process variation modeling using industry standard BSIM-CMG model
- R. Singh
- K. Aditya
- et al.
- 2016
- ICEE 2016
Analysis of systematic and random variation of gate-induced drain leakage in silicon-germanium channel pFET
- Vishal A. Tiwari
- Ch. L. N. Pavan
- et al.
- 2016
- ICEE 2016
Comparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET
- Ishita Jain
- Anshul Gupta
- et al.
- 2016
- ICEE 2016
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits
- C. J. Penny
- S. Gates
- et al.
- 2017
- IITC 2017
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016