Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyond
- Nicholas A. Lanzillo
- Koichi Motoyama
- et al.
- 2018
- IITC 2018
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58 results for Terence B. Hook
Advanced FDSOI design: The U-channel device for 7nm node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2017
- S3S 2017
Analysis of systematic and random variation of gate-induced drain leakage in silicon-germanium channel pFET
- Vishal A. Tiwari
- Ch. L. N. Pavan
- et al.
- 2016
- ICEE 2016
Comparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET
- Ishita Jain
- Anshul Gupta
- et al.
- 2016
- ICEE 2016
7-nm Nanowire FET process variation modeling using industry standard BSIM-CMG model
- R. Singh
- K. Aditya
- et al.
- 2016
- ICEE 2016
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits
- C. J. Penny
- S. Gates
- et al.
- 2017
- IITC 2017
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Nanowire FET design for 7-nm SOI-CMOS technology
- Ishita Jain
- Anil K. Bansal
- et al.
- 2015
- S3S 2015
Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
- Seong-Dong Kim
- Michael Guillorn
- et al.
- 2015
- S3S 2015