Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology

Abstract

Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realization of device-performance entitlement in high-performance and high-density chip designs is, therefore, of critical importance. In this paper, we present a quantitative performance evaluation of horizontal Nanosheet structures focused on key design styles as well as unique Nanosheet challenges such as gate-resistance. This analysis was performed with a fully developed design kit over a wide range of sub-7nm design, including various cell heights, as well as design features such as M1 power staples and performance-aware designs for smaller track cells.