SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
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23 results for Peter W. Cook
An 18 ns 56-bit multiply-adder circuit
- Robert K. Montoye
- P.W. Cook
- et al.
- 1990
- ISSCC 1990
Second-Generation RISC Floating Point with Multiply-Add Fused
- Erdem Hokenek
- Robert K. Montoye
- et al.
- 1990
- IEEE Journal of Solid-State Circuits
1 µm MOSFET VLSI Technology: Part III-Logic Circuit Design Methodology and Applications
- Darryl R. Freedman
- Stanley E. Schuster
- et al.
- 1979
- IEEE JSSC
1 μm MOSFET VLSI Technology: Part Ill—Logic Circuit Design Methodology and Applications
- Peter W. Cook
- Stanley E. Schuster
- et al.
- 1979
- IEEE T-ED
1, μm MOSFET VLSI Technology: Part IV-Hot-Electron Design Constraints
- Tak H. Ning
- Peter W. Cook
- et al.
- 1979
- IEEE JSSC
1 µm MOSFET VLSI Technology: Part 11—Device Designs and Characteristics for High-Performance Logic Applications
- Robert H. Dennard
- Fritz H. Gaensslen
- et al.
- 1979
- IEEE T-ED
1 µm MOSFET VLSI Technology: Part II-Device Designs and Characteristics for High-Performance Logic Applications
- Robert H. Dennard
- Fritz H. Gaensslen
- et al.
- 1979
- IEEE JSSC
1 μm MOSFET VLSI Technology: Part IV—Hot-Electron Design Constraints
- Tak H. Ning
- Peter W. Cook
- et al.
- 1979
- IEEE T-ED
A Study in the Use of PLA-Based Macros
- Peter W. Cook
- Chung W. Ho
- et al.
- 1979
- IEEE JSSC