Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5Ghz
- S.E. Schuster
- W. Reohr
- et al.
- 2000
- ISSCC 2000
Publications
Date
Featured collections
Popular topics
23 results for Peter W. Cook
SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
An 18 ns 56-bit multiply-adder circuit
- Robert K. Montoye
- P.W. Cook
- et al.
- 1990
- ISSCC 1990
1 µm MOSFET VLSI Technology: Part III-Logic Circuit Design Methodology and Applications
- Darryl R. Freedman
- Stanley E. Schuster
- et al.
- 1979
- IEEE JSSC
1 µm MOSFET VLSI Technology: Part II-Device Designs and Characteristics for High-Performance Logic Applications
- Robert H. Dennard
- Fritz H. Gaensslen
- et al.
- 1979
- IEEE JSSC
1, μm MOSFET VLSI Technology: Part IV-Hot-Electron Design Constraints
- Tak H. Ning
- Peter W. Cook
- et al.
- 1979
- IEEE JSSC
A Study in the Use of PLA-Based Macros
- Peter W. Cook
- Chung W. Ho
- et al.
- 1979
- IEEE JSSC
Comparison of Mosfet Logic Circuits
- Peter W. Cook
- Dale L. Critchlow
- et al.
- 1973
- IEEE JSSC
Automatic Artwork Generation for Large Scale Integration
- Peter W. Cook
- Wilm E. Donath
- et al.
- 1967
- IEEE JSSC
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ESSCIRC 2003