A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2014
- IEEE JSSC
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60 results for John F. Bulzacchelli
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- John F. Bulzacchelli
- Christian Menolfi
- et al.
- 2012
- IEEE JSSC
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing driftsin 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2012
- IEEE JSSC
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation
- Kevin Tien
- Ken Inoue
- et al.
- 2022
- DATE 2022
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS
- Miguel E. Perez
- Michael A. Sperling
- et al.
- 2019
- CICC 2019
A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
- Gautam Gangasani
- John F. Bulzacchelli
- et al.
- 2017
- VLSI Circuits 2017
A 32Gb/s, 4.7pJ/bit optical link with-11.7dBm sensitivity in 14nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2017
- VLSI Circuits 2017
A 28GHz SiGe BiCMOS phase invariant VGA
- Bodhisatwa Sadhu
- John F. Bulzacchelli
- et al.
- 2016
- RFIC 2016
A 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array
- Benjamin G. Lee
- Renato Rimolo-Donadio
- et al.
- 2015
- OFC 2015