On-chip decoupling capacitor optimization for high-performance VLSI design
- Howard H. Chen
- S.E. Schuster
- 1995
- VLSI-TSA 1995
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28 results for S.E. Schuster
3.5ns CMOS 64K ECL RAM at 77°K
- S.E. Schuster
- T.I. Chappell
- et al.
- 1988
- VLSI Circuits 1988
6.2 ns 64Kb CMOS RAM with ECL interfaces
- T.I. Chappell
- S.E. Schuster
- et al.
- 1988
- VLSI Circuits 1988
A high performance liquid-nitrogen CMOS SRAM technology
- J.Y.-C. Sun
- S. Klepner
- et al.
- 1988
- ESSDERC 1988
Laser personalization of integrated circuits
- S.E. Schuster
- P.W. Cook
- 1989
- Proceedings of SPIE 1989
Fast low power eDRAM hierarchical differential sense amplifier
- Stanley E. Schuster
- Richard E. Matick
- 2009
- IEEE Journal of Solid-State Circuits
Connections and disconnections on integrated circuits using nanosecond laser pulses
- P.W. Cook
- S.E. Schuster
- et al.
- 2008
- Applied Physics Letters
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Logic-based eDRAM: Origins and rationale for use
- Richard E. Matick
- Stanley E. Schuster
- 2005
- IBM J. Res. Dev
Low-power synchronous-to-asynchronous-to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
- Stanley E. Schuster
- Peter W. Cook
- 2003
- IEEE Journal of Solid-State Circuits