CMOS circuit technology for sub-ambient temperature operation
- I. Aller
- K. Bernstein
- et al.
- 2000
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference
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28 results for S.E. Schuster
On-chip decoupling capacitor optimization for high-performance VLSI design
- Howard H. Chen
- S.E. Schuster
- 1995
- VLSI-TSA 1995
SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture
- Terry I. Chappell
- Barbara A. Chappell
- et al.
- 1991
- IEEE Journal of Solid-State Circuits
A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces
- Terry I. Chappell
- Stanley E. Schuster
- et al.
- 1989
- IEEE Journal of Solid-State Circuits
6.2 ns 64Kb CMOS RAM with ECL interfaces
- T.I. Chappell
- S.E. Schuster
- et al.
- 1988
- VLSI Circuits 1988
3.5ns CMOS 64K ECL RAM at 77°K
- S.E. Schuster
- T.I. Chappell
- et al.
- 1988
- VLSI Circuits 1988
A high performance liquid-nitrogen CMOS SRAM technology
- J.Y.-C. Sun
- S. Klepner
- et al.
- 1988
- ESSDERC 1988
Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity
- Barbara A. Chappell
- Terry I. Chappell
- et al.
- 1988
- IEEE Journal of Solid-State Circuits
Stability and SER Analysis of Static RAM Cells
- Barbara Chappell
- Stanley E. Schuster
- et al.
- 1985
- IEEE Journal of Solid-State Circuits