G. Shahidi, J. Warnock, et al.
IBM J. Res. Dev
A 3.5-ns 64K CMOS RAM operated at 77 K has been described. The chip was fabricated in a dual 0.5-μm gate polysilicon process optimized for low-temperature operation. The design features asynchronous receivers capable of interfacing low-voltage ECL signal levels. Liquid-nitrogen operation of the RAM offers higher-speed operation than previously reported at the 64K level of integration for any technology.
G. Shahidi, J. Warnock, et al.
IBM J. Res. Dev
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H.J. Hoffmann, J. Woodall, et al.
Applied Physics Letters