New approach of local critical dimension uniformity improvement for via/contact hole etch with direct current superposition
- Emilia W. Hirsch
- Dominik Metzler
- et al.
- 2024
- JVSTB
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18 results for Logic Scaling
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- Hemanth Jagannathan
- Susan Fan
- et al.
- 2023
- SSDM 2023
LogInsights: Understanding and Extracting Information from Logs for Fast Fault Classification by Weak Supervision
- Suranjana Samanta
- Prateeti Mohapatra
- et al.
- 2023
- SSE 2023
Control of Plasma Etch Conditions through Pulsed, Cyclic, and QALE Processes for Advanced Node Applications
- 2023
- PESM 2023
A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology
- N. Jungmann
- Rajiv V. Joshi
- et al.
- 2023
- VLSI Technology 2023
TSV Stress Evolution Mapping using in-line Raman Spectroscopy
- Stefan Schoeche
- Daniel Schmidt
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023