Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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120 results at IEEE JSSC

1 Mb 0.41 μm²; 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- - Jing Li
  - Robert K. Montoye
  - et al.
- 2014
- IEEE JSSC
A 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
- - Lukas Kull
  - Thomas Toifl
  - et al.
- 2013
- IEEE JSSC
A 10 Gb/s 8-tap 6b 2-PAM/4-PAM tomlinson-harashima precoding transmitter for future memory-link applications in 22-nm SOI CMOS
- - Marcel Kossel
  - Thomas Toifl
  - et al.
- 2013
- IEEE JSSC
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- - Bodhisatwa Sadhu
  - Mark A. Ferriss
  - et al.
- 2013
- IEEE JSSC
An integral path self-calibration scheme for a dual-loop PLL
- - Mark Ferriss
  - Jean-Olivier Plouchart
  - et al.
- 2013
- IEEE JSSC
A millimeter-scale energy-autonomous sensor system with stacked battery and solar cells
- - Matthew Fojtik
  - Daeyeon Kim
  - et al.
- 2013
- IEEE JSSC
A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer
- - Noah Sturcken
  - Eugene J. O'Sullivan
  - et al.
- 2013
- IEEE JSSC
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- - John F. Bulzacchelli
  - Christian Menolfi
  - et al.
- 2012
- IEEE JSSC
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing driftsin 45-nm SOI CMOS technology
- - Gautam R. Gangasani
  - Chun-Ming Hsu
  - et al.
- 2012
- IEEE JSSC
Silicon photonic switches hybrid-integrated with CMOS drivers
- - Alexander V. Rylyakov
  - Clint L. Schow
  - et al.
- 2012
- IEEE JSSC