A. Bette, J.K. DeBrosse, et al.
VLSI Circuits 2003
A 16Mb Magnetic Random Access Memory (MRAM) is demonstrated in 0-18μm three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42μm2 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) cell, measures 79mm 2 and features a x16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.
A. Bette, J.K. DeBrosse, et al.
VLSI Circuits 2003
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