Conference paper
A Multiscale Workflow for Thermal Analysis of 3DI Chip Stacks
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025
Via metal corrosion during via CMP is one of the major process challenges for S/D (single damascene) interconnects. Thus, the detailed mechanism of via metal corrosion during via CMP have been investigated and a novel via process has been proposed to demonstrate via metal corrosion-free S/D interconnects. The via metal corrosion-free S/D interconnect could achieve improved viachain yield and enhanced EM (electromigration) performance compared to D/D (dual damascene) interconnect due to an ideal via profile and better Cu fill capability.
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025
Marcelo Amaral
OSSEU 2023
Indira Seshadri, Eric Miller, et al.
IEDM 2023
Nikoleta Iliakopoulou, Jovan Stojkovic, et al.
MICRO 2025