Accelerating High NA EUV Lithography Insertion for Interconnect Scaling and Beyond: Performance, Cost, and Future Prospects

Abstract

In this paper we will explore opportunities for insertion of High NA EUV in interconnect scaling. A comparative performance assessment of Cu Damascene sub-30 pitch interconnects patterned with single-expose 0.33 NA EUV and 0.55NA EUV will first allow us to understand the direct entitlement of High NA EUV with process window, stochastic defectivity, yield performance, and tip-to-tip resolution as key metrics. Additionally, this will identify challenges and opportunities as High NA EUV is deployed to pattern tighter pitch interconnects. Combined with this initial technical assessment, we will discuss a comparison of the cost of ownership analysis, focusing on 21nm pitch interconnects patterned with high NA EUV versus low NA EUV multipatterning. Building upon IBM’s ecosystem and history, we will demonstrate patterning and electrical performance through process co-optimization. We will then provide an early evaluation of ultimate interconnect viability at 18nm pitch and below. Finally, we will provide insights into insertion points beyond metal interconnects, where High NA EUV will help us address unique patterning challenges in logic scaling.