Andreas Kerber, D. Lipp, et al.
IEDM 2011
Variability induced by bias temperature instability is an increasing concern in aggressively scaled CMOS technologies. To assess the stochastic nature of the instability, we demonstrate that the recently introduced voltage ramp stress methodology properly captures the variance component and thus can be used to study stochastic effects related to transistor design and gate-stack processes. © 2013 IEEE.
Andreas Kerber, D. Lipp, et al.
IEDM 2011
Barry P. Linder, Eduard Cartier, et al.
IRPS 2009
Kisik Choi, Takashi Ando, et al.
ECS Meeting 2013
Siddarth Krishnan, Vijay Narayanan, et al.
IRPS 2012