Assembly and packaging of non-bumped 3D chip stacks on bumped substrates

Abstract

In this paper, a novel assembly and packaging approach is proposed for 3D/2.5D chip stacks based on bumped substrates. The thinned chips are stacked using thermal compression bonding with 'flat' metallization to reduce assembly complexity associated with conventional controlled-collapse-chip-connection (C4) solder bumps. Meanwhile, the laminate substrates are bumped with C4s using injected molten solder (IMS) processes. The pre-stacked chips are then assembled and packaged on the bumped laminates successfully.