Denny D. Tang, Tze-Chiang Chen, et al.
IEEE Electron Device Letters
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Denny D. Tang, Tze-Chiang Chen, et al.
IEEE Electron Device Letters
Jente B. Kuang, David H. Allen, et al.
IEEE Journal of Solid-State Circuits
Rajiv V. Joshi, Saibal Mukhopadhyay, et al.
ESSCIRC 2004
Rajiv V. Joshi, Keunwoo Kim, et al.
IEEE International SOI Conference 2003