CMOS and memories: From 100 nm to 10 nm!

Abstract

The dimensional limit where field-effect can still be gainfully employed is of the order of 10 nm. Other constraints that limit our use of field-effect are: random fluctuations in doping and thickness, gate insulator tunneling, electrostatic control of the channel, resistive and capacitive parasitics, device leakage and reliability, and the economics of any solution proposed. This contribution shows that physics allows devices that fulfill the need of microelectronics down to 10 nm length scale and summarizes experimental results that point out some of the directions that might be appropriate.