Dark field Double Dipole Lithography (DDL) for back-end-of-line processes

Abstract

The back-end-of-line metallization of a state-of-the-art CMOS process is the most critical level regarding the final density of the chip. While the gate level requires the most emphasis on linewidth control and critical dimension uniformity (CDU) of all lithography steps, the smallest pitch in the process is typically printed on the first metallization level. For this reason, a natural starting point for application of dipole lithography is not the gate level, which in many cases can be printed with quadrupole and other off-axis schemes with good process latitude, but the metal level with pitches that are typically between 10 and 25 % smaller than the gate pitch. If the same generation exposure tool is used for both gate and metallization levels, then a more aggressive off-axis illumination is needed for the metal level. In this paper, we investigate the application of double dipole lithography on the first metallization level (M1). We propose a simple bias to account for EMF effects compared to the thin mask approximation which is used in optical proximity correction. We discuss resist and BARC processes that are required at this pitch, and describe process windows. Using a 1.2 NA lithography system, we investigate the performance of this lithography technique at a pitch of 100 nm.