Development of vacuum underfill technology for a 3D chip stack

Abstract

We developed a vacuum underfill technology for 3D chip stacks and for flip chips in high performance system integration. We fabricated a 3D prototype chip stack using the vacuum underfill technology to apply the adhesive. The underfill was injected into each 6 νm gaps in a 3-layer chip stack and no voids were detected in acoustic microscopy images. Electrical tests and thermal reliability tests were used to measure the resistance of the vertical interconnections and the impact of the underfill. The results showed there was minimal difference in the average interconnection resistance of the chip stack with and without underfill. © 2011 IOP Publishing Ltd.