Siyu Koswatta, N. Mavilla, et al.
IEDM 2015
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Siyu Koswatta, N. Mavilla, et al.
IEDM 2015
Anshul Gupta, Charu Gupta, et al.
IEEE T-ED
Nauman Z. Butt, Jeffrey B. Johnson
IEEE Electron Device Letters
C. Pei, G. Wang, et al.
IEDM 2014