Samarth Agarwal, Terence B. Hook, et al.
IEEE T-ED
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Samarth Agarwal, Terence B. Hook, et al.
IEEE T-ED
Dechao Guo, G. Karve, et al.
VLSI Technology 2016
Ning Lu, Josef Watts, et al.
NSTI-Nanotech 2009
Jeffrey B. Johnson, Terence B. Hook, et al.
IEEE Electron Device Letters