Wilfried Haensch, Edward J. Nowak, et al.
IBM J. Res. Dev
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Wilfried Haensch, Edward J. Nowak, et al.
IBM J. Res. Dev
Ning Lu, Bill Dewey
CICC 2008
Anshul Gupta, Charu Gupta, et al.
IEEE T-ED
Ning Lu, Roger Booth, et al.
NSTI-Nanotech 2011