EUV mask challenges and requirements for ultimate single exposure interconnects

Abstract

Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.