PaperA Fully Scaled Submicrometer NMOS Technology Using Direct-Write E-Beam LithographyMatthew R. Wordeman, April M. Schweighart, et al.IEEE T-ED
PaperA 34 µ m2 DRAM Cell Fabricated with a 1 µm Single-Level Polycide FET TechnologyHu H. Chao, Robert H. Dennard, et al.IEEE Journal of Solid-State Circuits
PaperA perspective on today's scaling challenges and possible future directionsRobert H. Dennard, Jin Cai, et al.Solid-State Electronics
PaperGeneralized Scaling Theory and Its Application to a 1/4 micrometer MOSFET DesignRobert H. Dennard, Matthew R. WordemanIEEE T-ED
