Fast and Accurate Machine Learning Prediction of Back-End-of-Line Thermal Resistances in Backside Power Delivery and Chiplet Architectures

Heat dissipation is a critical issue in a backside power delivery network (BSPDN) chip package because heat from the powered transistors must travel through the signal interconnects (that have high thermal resistance) to the heat sink. Accurate modeling of BEOL stack thermal resistances is now required for better estimation of chip and package temperatures. Although analytical approaches for estimating BEOL interconnect layer thermal resistance have been developed, such methods show a large error of prediction or require a fitting factor based on heuristics to lower the discrepancy. This work demonstrates a novel approach of Machine Learning (ML) based fast thermal resistance prediction for back-end-of-line interconnect layers with finite element modeling accuracy. Our ML model predicts the thermal resistance of BEOL stacks with a mean absolute percentage error (MAPE) of less than 15%. This shows a remarkable improvement in accuracy in comparison to using a 1-D heat conduction analytical model, which showed a MAPE of 300%. Our framework is applied to a multi-scale thermal model of a backside power delivery network package for accurate hotspot temperature predictions and compared with the analytical model. We observe a significant difference in the maximum hotspot temperature in the chip due to the use of our accurate BEOL thermal resistances compared to the analytical properties.