Fast And Accurate Machine Learning Prediction of Back-End-Of-Line Thermal Resistances in Backside Power Delivery and Chiplet Architectures

Heat dissipation is a critical issue in enablement of advanced logic and packaging technologies including backside power delivery network (BSPDN) and 3D chiplet packaging architectures. Among the various thermal resistances in the junction-to-ambient heat dissipation pathway, it is widely acknowledged that the impact of the back-end-of-line (BEOL) thermal resistance can significantly increase the local junction temperature. As a result, accurate modeling of BEOL stack thermal resistances is required for better estimation of junction temperature, device performance and electromigration issues. However, finite element models including details of BEOL wiring are impractical to implement over areas larger than 100-1000μm2. Although analytical approaches for estimating BEOL stack thermal resistance have been developed, such methods show a large error of prediction or require a fitting factor based on heuristics to lower the discrepancy. In this work, we develop a Machine Learning (ML) framework that can rapidly and accurately predict the thermal resistance over large areas using the chip design layout, layer heights and material information as inputs. Our framework successfully captures the impact of various wire-wire connectivity features within and across BEOL levels, that are responsible for modulating the thermal transport. Our ML model was trained on finite element simulation results for a small set of BEOL structures that were sampled using an automated and systematic method. Once trained, our ML model is able to predict the thermal resistance of BEOL stacks with a mean absolute percentage error (MAPE) of less than 15%. This shows a remarkable improvement in accuracy over the usual analytical methods such as using series-parallel resistance networks, which showed an MAPE of 300%. Moreover, unlike these analytical models, our method can capture the effect of different types of via connectivity at the same overall metal density due to its ability to identify feature-property correlations within the 3D structure. To demonstrate the necessity of such a fast and accurate thermal resistance predictor, we performed thermal simulations of a BSPDN HPC package, where our ML algorithm was applied to obtain the spatially varying BEOL thermal resistance over the entire chip layout. A sub-modeling approach was used to estimate the local temperature rise in the high power-density logic core with a more detailed power density map as input. The results of this simulation were compared against two models using either a local metal density dependent analytical estimation of BEOL resistance or a single average BEOL thermal resistance over the entire chip. We observe a significant difference in both the temperature distribution and the highest junction temperature in the chip due to the use of our accurate BEOL thermal resistances compared to use of the analytical and average properties. In particular, the presence of the BEOL stack in the junction-to-ambient heat flow path in a BSPDN package leads to greater impact of BEOL stack thermal properties on the local temperature distribution and demonstrates the effectiveness of our modeling approach.