Graphite sheet embedded in an organic flip-chip package for heat spreading

In conventional flip chip semiconductor packages, heat removal and heat spreading have flowed through the chip back-side (the Si substrate). The typical heat removal and spreading structure consists of a first thermal interface material (TIM 1), a heat spreader or lid, a second TIM 2, and a heatsink or cold-plate. Many improvements in heatsink performance have been ongoing for decades, such as more efficient air-cooling, and single-phase liquid cooling. There have been recent studies on two-phase liquid cooling as well. In parallel, compliant direct-attach liquid-cooled heatsink solutions have been proposed to eliminate TIM 1 and a heat spreader. These studies aim to improve the heat removal and spreading performance by modification or removal of components in the thermal path. There have been many efforts in this area, with significant progress. In addition to conventional heat removal and spreading from the chip back-side, additional heat removal and spreading from the chip top-side (through the BEOL into the organic substrate) has also been considered, because conventional chip back-side heat removal and spreading will likely be performance-limiting at some point. We call this dual-sided chip cooling, and have studied it for potential solutions. In conventional flip-chip packages, an organic substrate is used for electrical power and signal delivery. The thermal performance of an organic substrate is poor, and is not typically considered. To enable use of this substrate for heat removal and spreading, a complex interdependency among electrical, thermal and thermo-mechanical must be solved. In this paper, heat spreading within an organic substrate using an integrated graphite sheet within the solder resist layer is proposed. Graphite has unique, anisotropic thermal conductivities, such as 1500 - 1700 W/mK (x, y) and 5 - 7 W/mK (z). The coefficient of thermal expansion (CTE) is also anisotropic, such as 23.9 ppm (x, y) and 0.07 ppm (z). If organic substrate warpage is an issue, it is also possible to locate the graphite sheet as a bottom layer. The conventional interconnect pitch is 150 m, and therefore 150 m pitch through-via holes in the graphite are necessary. The proposed fabrication process consists of 4 modules: (1) adhering the graphite sheet to the organic substrate; (2) patterning via-holes through the graphite; (3) applying solder resist in the via-holes for electrical insulation; and (4) applying pre-solder. For (2), we show promising results for via-hole patterning in graphite by a laser ablation process. Concerning thermo-mechanical performance, the elongation of a graphite sheet is measured by a pull-test as 1%. With this result and considering the elastic moduli, it is therefore considered that a thin graphite sheet, such as 25 m thick, will not influence the organic substrate modulus and CTE. Regarding electrical performance, a graphite sheet is electrically conductive, and we therefore must consider induced eddy currents and capacitive coupling from transverse, high-frequency signals flowing through the graphite vias. The induced currents vs. graphite sheet thickness and conductor-to-via-sidewall spacings were modeled. While the induced currents may be of order ~1%, minimizing them requires minimizing graphite thickness and maximizing conductor-to-via-sidewall spacings. These are trade-offs with thermal performance, and so must be co-optimized. As one example of our thermal simulation results, in a two-chip-stack configuration and with chip size of 20 mm x 20 mm, an assumed heat density of 250 W/cm2 at the center area of a bottom chip (0.5 mm x 0.5 mm area), our proposed graphite sheet structure can reduce the maximum chip temperature by 4.8°C (from 69.2°C to 64.4°C). For hardware validation, simple thermal experiments using a graphite sheet, a heater and a thermocouple were performed, and the correlation between the simulated temperatures and the measured ones is discussed.