Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
Comparison of junctionless and conventional nanowire FETs is presented. Our numerical simulation results suggest that though the junctionless device suffers low drive current due to its accumulation nature, it has an advantage in scalability. Relaxed wire diameter requirement is predicted for the junctionless case. More interestingly, it shows a great potential in ultra-low power subthreshold logic application due to superior speed, as compared with the conventional structure. ©2010 IEEE.
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
G. Wang, Carl Radens, et al.
IEEE International SOI Conference 2010
Phil Oldiges, Kenneth P. Rodbell, et al.
IEEE International SOI Conference 2010
Yi-Bo Liao, Meng-Hsueh Chiang, et al.
Microelectronics Journal