S. Narasimha, P. Chang, et al.
IEDM 2012
The transition to multicore computing demands more embedded cache memories. Incorporating high performance eDRAMs into the cache hierarchy is an attractive solution. In this paper, we discuss the roles of SRAM, eDRAM and eFUSE OTPROM in a high performance SOI chip. ©2010 IEEE.
S. Narasimha, P. Chang, et al.
IEDM 2012
Phil Oldiges, Kenneth P. Rodbell, et al.
IEEE International SOI Conference 2010
C. Pei, G. Wang, et al.
IEDM 2014
Azeez Bhavnagarwala, Stephen Kosonocky, et al.
IEDM 2005