Hu H. Chao, Robert H. Dermard, et al.
ISSCC 1981
This paper reports a 32-bit single-chip microprocessor that directly implements 102 System/370 instructions and supports the emulation of the rest of the instructions. It is fabricated using a 2-µm polysilicon gate NMOS technology with two levels of aluminum. The chip is 10×10 mm2 with 200 000 transistor sites. It is designed for a 10-MHz clock at worst case and has been operated at 18 MHz with 3-W power dissipation. The design and verification methodologies and the testing consideration are also described. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.
Hu H. Chao, Robert H. Dermard, et al.
ISSCC 1981
Nicky C.C. Lu, Hu H. Chao, et al.
IEEE Journal of Solid-State Circuits
Nicky Chau-Chun Lu, Hu H. Chao
IEEE Journal of Solid-State Circuits
Nicky C. C. Lu, Hu H. Chao, et al.
IEEE Journal of Solid-State Circuits