Partially-depleted SOI compact model - formulation and parameter extraction

Abstract

As SOI technology advances into mainstream, an accurate and predictive compact model is necessary to ensure the success of VLSI chip design. This paper describes a compact model which contributes to the successful implementation of the sophiscated 660 MHz 64-bit PowerPC at its first design. This model captures all important SOI specific device characteristics and circuit behavior properly. The parameter extraction methodology, which is essential in achieving a highly accurate model, will be discussed. Verification results using a 0.18 um (1.5 V) high performance SOI CMOS technology will be presented.