Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
- Sarunya Bangsaruntip
- K. Balakrishnan
- et al.
- 2013
- IEDM 2013
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51 results for Jeffrey W. Sleight
Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs
- Amlan Majumdar
- Sarunya Bangsaruntip
- et al.
- 2012
- IEDM 2012
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling
- S. Bangsaruntip
- G.M. Cohen
- et al.
- 2009
- IEDM 2009
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Highly Manufacturable 40-50 GHz VCOs in a 120nm System-on-Chip SOI Technology
- Jonghae Kim
- Jean-Olivier Plouchart
- et al.
- 2003
- IEDM 2003
Controlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999