Ernest Y Wu, Takashi Ando, et al.
IEDM 2023
In this work we demonstrate cryogenic HEMTs with highly scaled gate footprints, down to for a single gate finger, and investigate the impact of footprint scaling on device performance. The In channel devices show and together with a noise indication factor at , which is a record-high combination of high-frequency and low-noise performance. The performance is enabled by heterostructure engineering, resulting in ultra-low together with a minimum subthreshold swing . These results show that cryogenic III-V HEMT technology can provide excellent performance at scaled footprints for readout in future high-density quantum systems.
Ernest Y Wu, Takashi Ando, et al.
IEDM 2023
Lin Dong, Steven Hung, et al.
VLSI Technology 2021
Katja-Sophia Csizi, Emanuel Lörtscher
Frontiers in Neuroscience
Pritish Narayanan, Sidney Tsai
VLSI Technology and Circuits 2025