Variable-size shallow trench isolation (STI) technology with diffused sidewall doping for submicron CMOS

Abstract

A shallow trench isolation (STI) technology, RIE (reactive ion etching), CVD (chemical vapor deposition) oxide fill, and planarization are used to realize lithography-limited, submicron device and isolation dimensions. A novel boron diffusion technique is used for nMOSFET field doping, so that the parasitic sidewall inversion (leakage) problem is eliminated. It is shown that both the channel width bias and the narrow channel effect are greatly reduced in the STI technology. The diffused field also allows the boron doping to be self-aligned to the n-well with a single masking step in CMOS. STI is used in conjunction with a MINT (merged isolation and node trench) cell in 16-Mb DRAM (dynamic random access memory) technology.