Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

Abstract

In this letter, we present a novel junction integration scheme that enables vertical transistors to have high performance, low leakage, and easy scalability. Controlled solid-phase diffusion is used to form the vertically self-aligned buried strap junction of the vertical transistor. The electric field at the capacitor node junction is carefully optimized by creating a graded junction profile, resulted from a combination of out-diffusion from Arsenic-doped poly-silicon and Phosphorus-doped oxide. The Phosphorus-doped oxide serves as the dopant source for the vertical lightly doped drain, as well as the spacer for the high dose junctions. Integration of the self-aligned junctions into a vertical transistor dynamic random access memory (DRAM) process flow is presented. Significant improvement in the retention characteristics of a 256-Mb DRAM product confirms the applicability of this newly developed junction integration scheme for future DRAM generations.