J.C. Marinace
JES
Short, medium, and long on-chip interconnections having linewidths of 0.45-52 μ are analyzed in a five-metallayer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction. © 1997 IEEE.
J.C. Marinace
JES
Shaoning Yao, Wei-Tsu Tseng, et al.
ADMETA 2011
Ronald Troutman
Synthetic Metals
A. Nagarajan, S. Mukherjee, et al.
Journal of Applied Mechanics, Transactions ASME