High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
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21 results for S. Subbanna
High-performance silicon-germanium technology
- Seshadri Subbanna
- Greg Freeman
- et al.
- 2005
- DRC 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2003
- IEEE Electron Device Letters
Foundation of rf CMOS and SiGe BiCMOS technologies
- James S. Dunn
- David C. Ahlgren
- et al.
- 2003
- IBM J. Res. Dev
A comprehensive simulation study of strained-Si/SiGe nMODFET scaling for RF applications
- Qiqing Christine Ouyang
- S.J. Koester
- et al.
- 2002
- SISPAD 2002
A 4.2-ps ECL ring-oscillator in a 285-GHz f MAX SiGe technology
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2002
- IEEE Electron Device Letters
40-Gb/s circuits built from a 120-GHz f T SiGe technology
- Greg Freeman
- Mounir Meghelli
- et al.
- 2002
- IEEE Journal of Solid-State Circuits
Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology
- B. Jagannathan
- M. Khater
- et al.
- 2002
- IEEE Electron Device Letters
50-200 GHz silicon-germanium heterojunction bipolar transistor BICMOS technology and a computer-aided design environment for 2-50+GHz very large-scale integration mixed-signal ICs
- Seshadri Subbanna
- Gregory Freeman
- et al.
- 2002
- Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers