Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips
- S. Voldman
- D. Hui
- et al.
- 2000
- Journal of Electrostatics
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31 results for F. Assaderaghi
Partially-depleted SOI compact model - formulation and parameter extraction
- S.K.H. Fung
- L. Wagner
- et al.
- 2000
- VLSI Technology 2000
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips
- S. Voldman
- D. Hui
- et al.
- 1999
- EOS/ESD 1999
0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
A dynamic body discharge technique for SOI circuit applications
- J.B. Kuang
- M.J. Saccamango
- et al.
- 1999
- IEEE International SOI Conference 1999
Electrostatic discharge protection in silicon-on-insulator technology
- S. Voldman
- D. Hui
- et al.
- 1999
- IEEE International SOI Conference 1999
A body-contact SOI MOSFET model for circuit simulation
- P. Su
- S.K.H. Fung
- et al.
- 1999
- IEEE International SOI Conference 1999
Circuit styles and strategies for CMOS VLSI design on SOI
- F. Assaderaghi
- 1999
- ISLPED 1999