Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design
- W. Chen
- W. Hwang
- et al.
- 2001
- ISLPED 2001
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31 results for Stephen Kosonocky
Enhanced multi-threshold (MTCMOS) circuits using variable well bias
- S.V. Kosonocky
- M.J. Immediato
- et al.
- 2001
- ISLPED 2001
Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
Eight-issue tree-VLIW processor for dynamic binary translation
- Kemal Ebcioglu
- Jason Fritts
- et al.
- 1998
- ICCD 1998
Reducing ground-bounce noise and stabilizing the data-retention voltage of power-gating structures
- Suhwan Kim
- Chang Jun Choi
- et al.
- 2008
- IEEE Transactions on Electron Devices
A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2007
- IEEE TCAS-II
On-chip synchronous communication between clock domains with quotient frequencies
- V. Sathe
- M.C. Papaefthymiou
- et al.
- 2007
- Electronics Letters
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
- Phillip Chin
- Charles A. Zukowski
- et al.
- 2005
- Integration, the VLSI Journal
Application of an SOI 0.12-μm CMOS technology to SoCs with low-power and high-frequency circuits
- Jean-Olivier Plouchart
- Noah Zamdmer
- et al.
- 2003
- IBM J. Res. Dev