A novel integration scheme for self-aligend Ru topvia as post-Cu alternative metal interconnects
- K. Motoyama
- D. Metzler
- et al.
- 2023
- IITC/MAM 2023
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14 results for Chanro Park
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization
- N. Gong
- Malte J. Rasch
- et al.
- 2022
- IEDM 2022
Improved Air Spacer for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- IEEE Transactions on Electron Devices
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Plasma treatment effect on gate stack electrical properties
- Tao Li
- Chanro Park
- et al.
- 2018
- ANTS 2018
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017