External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology
- Oleg Gluschenkov
- Heng Wu
- et al.
- 2018
- IEDM 2018
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15 results for A. Carr
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Study of titanium nitride underlayer properties and its influence on tungsten growth
- Shanti Pancharatnam
- J. Wynne
- et al.
- 2018
- ASMC 2018
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
- Nicolas Breil
- A. Carr
- et al.
- 2017
- VLSI Technology 2017
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
- Zuoguang Liu
- Oleg Gluschenkov
- et al.
- 2017
- VLSI Technology 2017
Contacts in advanced CMOS: History and emerging challenges
- Christian Lavoie
- Praneet Adusumilli
- et al.
- 2017
- ECS Meeting 2017 - New Orleans
Formation and microstructure of thin Ti silicide films for advanced technologies
- Praneet Adusumilli
- A. Carr
- et al.
- 2016
- IITC/AMC 2016
Tungsten and cobalt metallization: A material study for MOL local interconnects
- Vimal Kamineni
- Mark Raymond
- et al.
- 2016
- IITC/AMC 2016