Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
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17 results for Vimal Kamineni
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Validity and Application of the TCR Method to MOL contactS
- E. Milosevic
- Vimal Kamineni
- et al.
- 2018
- IITC 2018
Future on-chip interconnect metallization and electromigration
- C. K. Hu
- James Kelly
- et al.
- 2018
- IRPS 2018
Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires
- C. K. Hu
- James Kelly
- et al.
- 2017
- IITC 2017
Middle of line RC performance study at the 7 nm node
- Susan Su Chen Fan
- James H.-C. Chen
- et al.
- 2017
- IITC 2017
Experimental study of nanoscale Co damascene BEOL interconnect structures
- James Kelly
- James H.-C. Chen
- et al.
- 2016
- IITC/AMC 2016
Formation and microstructure of thin Ti silicide films for advanced technologies
- Praneet Adusumilli
- A. Carr
- et al.
- 2016
- IITC/AMC 2016