External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology
- Oleg Gluschenkov
- Heng Wu
- et al.
- 2018
- IEDM 2018
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10 results for Chengyu Niu
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys
- Oleg Gluschenkov
- Zuoguang Liu
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Tungsten and cobalt metallization: A material study for MOL local interconnects
- Vimal Kamineni
- Mark Raymond
- et al.
- 2016
- IITC/AMC 2016
Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study
- Nicholas A. Lanzillo
- H. Dixit
- et al.
- 2018
- Journal of Applied Physics
First-Principles Investigations of TiGe/Ge Interface and Recipes to Reduce the Contact Resistance
- H. Dixit
- Chengyu Niu
- et al.
- 2017
- IEEE T-ED
Impact of surface preparation for n-type Si:P and p-type SiGe:B semiconductors on low resistance silicide contacts
- A. Carr
- B. Peethala
- et al.
- 2017
- Microelectronic Engineering