On the systematic analysis of ring-delay performance using statistical behavior model
- Q. Liang
- B. Greene
- et al.
- 2009
- ISDRS 2009
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48 results for E. Nowak
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Improved effective switching current (Ieff+) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation
- Xiaojun Yu
- Shu-Jen Han
- et al.
- 2008
- IEDM 2008
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2007
- VLSID 2007
High performance CMOS variability in the 65nm regime and beyond
- Sani Nassif
- Kerry Bernstein
- et al.
- 2007
- IEDM 2007
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
Self-consistent and efficient electro-thermal analysis for poly/metal gate FinFETs
- Satish Kumar
- Rajiv V. Joshi
- et al.
- 2006
- IEDM 2006
Silicon CMOS devices beyond scaling
- Wilfried Haensch
- Edward J. Nowak
- et al.
- 2006
- IBM J. Res. Dev
High-performance CMOS variability in the 65-nm regime and beyond
- Kerry Bernstein
- David J. Frank
- et al.
- 2006
- IBM J. Res. Dev