Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
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48 results for E. Nowak
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
CMOS devices below 0.1 μm: How high will performance go?
- Yuan Taut
- E. Nowak
- 1997
- IEDM 1997
The effect of change of voltage acceleration on temperature activation of oxide breakdown for ultrathin oxides
- E. Wu
- J.M. McKenna
- et al.
- 2001
- IEEE Electron Device Letters
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
SOI FinFET versus bulk FinFET for 10nm and below
- Terence B. Hook
- F. Allibert
- et al.
- 2014
- S3S 2014
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013
Revisiting the impact on sub-threshold regions in uniaxially-strained FETs
- M.H. Na
- K. Mcstay
- et al.
- 2013
- CSTIC 2013
On the systematic analysis of ring-delay performance using statistical behavior model
- Q. Liang
- B. Greene
- et al.
- 2009
- ISDRS 2009
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009