Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Publications
Date
Featured collections
Popular topics
55 results for John Arnold
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
High reliability 32 nm Cu/ULK BEOL based on PVD CuMn seed, and its extendibility
- Takeshi Nogami
- Tibor Bolom
- et al.
- 2010
- IEDM 2010
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Mobility scaling in short-channel length strained Ge-on-insulator P-MOSFETs
- Stephen W. Bedell
- Amlan Majumdar
- et al.
- 2008
- IEEE Electron Device Letters
Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks
- V. Narayanan
- K. Maitra
- et al.
- 2006
- IEEE Electron Device Letters
Overlay Performance in Permanent Bonded Wafer Integration Schemes
- Nathan Ip
- Michael Belyansky
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Electrical validation of the integration of 193i and DSA for sub-20nm metal cut patterning
- Chi Chun Liu
- Richard Farrell
- et al.
- 2019
- MEMS/NEMS/MOEMS 2019
Introduction of pre-etch deposition techniques in EUV patterning
- Xun Xiang
- Genevieve Beique
- et al.
- 2018
- SPIE Advanced Lithography 2018