220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- T. Kirihata
- M. Gall
- et al.
- 1998
- ISSCC 1998
Publications
Date
Featured collections
Popular topics
10 results for Hing Wong
A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)
- L.A. Nesbit
- J. Alsmeier
- et al.
- 1993
- IEDM 1993
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Flexible test mode design for DRAM characterization
- H. Wong
- T. Kirihata
- et al.
- 1996
- VLSI Circuits 1996
CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-/spl μ/m CMOS technology
- H. Wong
- R. Chang
- et al.
- 1998
- IEEE Transactions on Electron Devices
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- Toshiaki Kirihata
- Martin Gall
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
Flexible test mode approach for 256-Mb DRAM
- Toshiaki Kirihata
- Hing Wong
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Fault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEEE Journal of Solid-State Circuits
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ
- Yohji Watanabe
- Hing Wong
- et al.
- 1996
- IEICE Transactions on Electronics
Fault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEICE Transactions on Electronics