Reliability benefits of a metallic liner in confined PCM
- Wanki Kim
- S. Kim
- et al.
- 2018
- IRPS 2018
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58 results for A. Ray
A Double-Data-Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read-Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
- H. Lung
- C. Miller
- et al.
- 2016
- IMW 2016
A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application
- W. Chien
- Yung-Han Ho
- et al.
- 2015
- VLSI Technology 2015
A scalable volume-confined phase change memory using physical vapor deposition
- S.C. Lai
- S. Kim
- et al.
- 2013
- VLSI Technology 2013
Optimization of programming current on endurance of phase change memory
- Sangbum Kim
- Pei-Ying Du
- et al.
- 2012
- VLSI-TSA 2012
Effective schottky barrier lowering for contact resistivity reduction using silicides as diffusion sources
- Zhen Zhang
- F. Pagette
- et al.
- 2010
- VLSI-TSA 2010
Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm
- N. Tega
- H. Miki
- et al.
- 2009
- VLSI Technology 2009
Silicon-on-insulator MOSFETs with hybrid crystal orientations
- M. Yang
- K.K. Chan
- et al.
- 2006
- VLSI Technology 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology
- Jean-Olivier Plouchart
- Jonghae Kim
- et al.
- 2003
- ESSCIRC 2003