Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits
- C.T. Chuang
- R.V. Joshi
- et al.
- 2003
- ISQED 2003
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85 results for Ruchir Puri
Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits
- C.T. Chuang
- R. Puri
- 2002
- IEEE International SOI Conference 2002
Fast and accurate wire delay estimation for physical synthesis of large ASICs
- Ruchir Puri
- David S. Kung
- et al.
- 2002
- GLSVLSI 2002
Measurement of history effect in PD/SOI single-ended CPL circuit
- Keith A. Jenkins
- R. Puri
- et al.
- 2001
- IEEE International SOI Conference 2001
SOI digital circuits: design issues
- R. Puri
- C.T. Chuang
- 2000
- VLSID 2000
Optimal P/N width ratio selection for standard cell libraries
- D.S. Kung
- R. Puri
- 1999
- ICCAD 1999
Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits
- R. Puri
- C.T. Chuang
- 1998
- IEEE International SOI Conference 1998
Design issues in mixed static-domino circuit implementations
- 1998
- ICCD 1998
Logic optimization by output phase assignment in dynamic logic synthesis
- R. Puri
- Andrew Bjorksten
- et al.
- 1996
- ICCAD 1996
NeuNetS: An Automated Synthesis Engine for Neural Network Design
- Atin Sood
- Benjamin Elder
- et al.
- 2019
- arXiv