Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
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45 results for Rama Divakaruni
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
- J. Beintner
- Y. Li
- et al.
- 2004
- IEEE Electron Device Letters
On the retention time distribution of dual-channel vertical DRAM technologies
- J. Beintner
- Y. Li
- et al.
- 2003
- VLSI-TSA 2003
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Jack A. Mandelman
- Robert H. Dennard
- et al.
- 2002
- IBM J. Res. Dev