3-D Die Stacking with 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
- Katsuyuki Sakuma
- Mukta Farooq
- et al.
- 2021
- IEEE Transactions on CPMT
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45 results for Rama Divakaruni
Improved Air Spacer for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- IEEE Transactions on Electron Devices
OFF-State Leakage and Performance Variations Associated with Germanium Preamorphization Implant in Silicon-Germanium Channel pFET
- Vishal A. Tiwari
- Rama Divakaruni
- et al.
- 2018
- IEEE T-ED
Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages
- Vishal A. Tiwari
- Rama Divakaruni
- et al.
- 2016
- Japanese Journal of Applied Physics
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Jack A. Mandelman
- Robert H. Dennard
- et al.
- 2002
- IBM J. Res. Dev