Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates
- L.K. Han
- S.W. Crowder
- et al.
- 1997
- IEDM 1997
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21 results for Shih Hsien Lo
Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors
- Jae-Joon Kim
- Aditya Bansal
- et al.
- 2009
- IEEE Electron Device Letters
Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's
- S.H. Lo
- D.A. Buchanan
- et al.
- 1997
- IEEE Electron Device Letters
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
- Jinwook Oh
- Sae Kyu Lee
- et al.
- 2020
- VLSI Circuits 2020
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference
- Bruce Fleischer
- Sunil Shukla
- et al.
- 2018
- VLSI Circuits 2018
Variability and power management in sub-100nm SOI technology for reliable high performance systems
- Koushik Das
- Kerry Bernstein
- et al.
- 2008
- IEEE International SOI Conference 2008
Power-gating schemes for Ultra-Thin SOI (UTSOI) circuits in hybrid SOI-epitaxial CMOS structures
- Shih-Hsien Lo
- Koushik K. Das
- et al.
- 2007
- VLSI-DAT 2007
High performance MTCMOS technique for leakage reduction in hybrid SOI-epitaxial technologies with enhanced-mobility PFET header
- Koushik K. Das
- Shih-Hsien Lo
- et al.
- 2006
- VLSID/Embedded 2006
Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2005
- ISQED 2005
Analysis and design of digital CMOS circuits in hybrid SOI-epitaxial technology with different crystal orientations
- Koushik K. Das
- Shih-Hsien Lo
- et al.
- 2004
- IEEE International SOI Conference 2004