Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
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62 results for Dechao Guo
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates
- Shu-Jen Han
- Josephine Chang
- et al.
- 2010
- IEDM 2010
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- Dechao Guo
- Kathryn Schonenberg
- et al.
- 2009
- MRS Fall Meeting 2009
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
On the difference of temperature dependence of metal gate and poly gate SOI MOSFET threshold voltages
- Shu-Jen Han
- Xinlin Wang
- et al.
- 2008
- IEDM 2008
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
High performance gate first HfSiON dielectric satisfying 45nm node requirements
- M.A. Quevedo-Lopez
- S. Krishnan
- et al.
- 2005
- IEDM 2005
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022