Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Publications
6 results for Susan Fan
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- Hemanth Jagannathan
- Susan Fan
- et al.
- 2023
- SSDM 2023
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022